SPECIALIZED ENGINEERING SERVICES
Engineering Excellence from Architecture to Silicon
Complex Analog and Mixed Signal IP Design Services, from concept to
silicon, and product engineering. Every KPI is optimized for a product with
special focus on quality and predictability.
120+
Years Combined Experience
50+
Silicon Products Delivered
10+
Process Nodes
100+
Successful Tape-outs
Engagement Models Tailored to Your Program
Flexible, transparent, and quality-driven engagement frameworks to meet your exact IP
development needs.
Orientation Change
Transforming the Base IP to different orientations to fit specific
layout requirements.
Aspect Ratio adjustments
Complete Orientation flipping
Configuration (e.g., No of Lanes)
Same or Better KPI (Power performance Area) than original IP
Same or different process node
Process porting
Derivative of existing IP to different foundry processes achieving
same or better KPIs.
Any Process to Any Process Port
Improved KPI (Power, Perf, Area)
CO-VAL with existing Phy
Addressing process driven design changes
Along with Physical (Orientation/Aspect Ratio) change
Custom Feature Addition
Feature addition, and deep Performance/Power/Area Optimization
for existing designs.
Incorporation of product driven Logic/Circuit features
Post Silicon driven ECO’s
DFT & SCAN improvements
Improvement of one or more IP KPI
Built to spec
New IP development based on spec/requirements from
Architecture to Tapeout.
End to End ownership (Arch to implementation to product
Engg)
Post-Si Debug and productization
Complete FW and package development
IP KPI improvements
Portfolio Progression
2026
2027
2028
IP
TURNKEY-CUSTOM IP
BASE IP
Process Port
Orientation Change
Feature Addition
IP Optimization
Base IP
UCIe
2026
2026
2026
2026
2028
PCIe
2026
2026
2026
2026
2028
DDR/HBM
2026
2026
2026
2026
2028
PLL
2027
2027
2027
2027
2028
GPIO
2027
2027
2027
2027
2027
Turnkey Custom IP:
Base IP modifications for Process/PHYS change, Feature add,
PPA improvements/etc.
Turnkey Base IP:
New IP based on spec/requirements given by customer on
targeted process and PPA.
Customer Engagement Model
A collaborative model that drives transparency, efficiency, and successful IP delivery.
1. DESIGN ENABLER
Client Responsibilities
Compute
Provide compute infrastructure (Login Access, Machines,
Memory)
Tools and Methodology
Provide EDS tools and methodology (Licenses, Setup files)
Technology Enablers
Provide Technology Collaterals (PDK, Library, etc)
NovaRays Responsibilities
Infrastructure Utilization
Utilizes provided compute infrastructure for development
Tool Execution
Uses provided EDS tools and methodology for IP development
IP Development
Leverages technology collaterals for IP development
2. RECEIVABLES & DELIVERABLES
Client Responsibilities
Pre-Design Collaterals
Provide Source IP Collaterals (Schematic, RTL, Layout, Timing
Constraints, IntGuide)
NovaRays Responsibilities
Milestone Delivery
Deliver IP Collaterals for all milestones (Netlist, GDS, RTL,
IntGuide, MAS, FW Doc)
A collaborative model that drives transparency, efficiency, and successful IP delivery.
Nova
Rays
Semi
© 2026 NovaRays Semi. All rights reserved.
Precision Engineering & Semi-Conductor Systems.
© 2026 NovaRays Semi. All rights reserved.
Precision Engineering & Semi-Conductor Systems.
SPECIALIZED ENGINEERING SERVICES
Engineering Excellence from Architecture to Silicon
Complex Analog and Mixed Signal IP Design Services, from concept to
silicon, and product engineering. Every KPI is optimized for a product with
special focus on quality and predictability.
120+
Years Combined Experience
50+
Silicon Products Delivered
10+
Process Nodes
100+
Successful Tape-outs
Engagement Models Tailored to Your Program
Flexible, transparent, and quality-driven engagement frameworks to meet your exact IP
development needs.
Orientation Change
Transforming the Base IP to different orientations to fit specific
layout requirements.
Aspect Ratio adjustments
Complete Orientation flipping
Configuration (e.g., No of Lanes)
Same or Better KPI (Power performance Area) than original IP
Same or different process node
Process porting
Derivative of existing IP to different foundry processes achieving
same or better KPIs.
Any Process to Any Process Port
Improved KPI (Power, Perf, Area)
CO-VAL with existing Phy
Addressing process driven design changes
Along with Physical (Orientation/Aspect Ratio) change
Custom Feature Addition
Feature addition, and deep Performance/Power/Area Optimization
for existing designs.
Incorporation of product driven Logic/Circuit features
Post Silicon driven ECO’s
DFT & SCAN improvements
Improvement of one or more IP KPI
Built to spec
New IP development based on spec/requirements from
Architecture to Tapeout.
End to End ownership (Arch to implementation to product
Engg)
Post-Si Debug and productization
Complete FW and package development
IP KPI improvements
Portfolio Progression
2026
2027
2028
IP
TURNKEY-CUSTOM IP
BASE IP
Process Port
Orientation Change
Feature Addition
IP Optimization
Base IP
UCIe
2026
2026
2026
2026
2028
PCIe
2026
2026
2026
2026
2028
DDR/HBM
2026
2026
2026
2026
2028
PLL
2027
2027
2027
2027
2028
GPIO
2027
2027
2027
2027
2027
Turnkey Custom IP:
Base IP modifications for Process/PHYS change, Feature add,
PPA improvements/etc.
Turnkey Base IP:
New IP based on spec/requirements given by customer on
targeted process and PPA.
Customer Engagement Model
A collaborative model that drives transparency, efficiency, and successful IP delivery.
1. DESIGN ENABLER
Client Responsibilities
Compute
Provide compute infrastructure (Login Access, Machines,
Memory)
Tools and Methodology
Provide EDS tools and methodology (Licenses, Setup files)
Technology Enablers
Provide Technology Collaterals (PDK, Library, etc)
NovaRays Responsibilities
Infrastructure Utilization
Utilizes provided compute infrastructure for development
Tool Execution
Uses provided EDS tools and methodology for IP development
IP Development
Leverages technology collaterals for IP development
2. RECEIVABLES & DELIVERABLES
Client Responsibilities
Pre-Design Collaterals
Provide Source IP Collaterals (Schematic, RTL, Layout, Timing
Constraints, IntGuide)
NovaRays Responsibilities
Milestone Delivery
Deliver IP Collaterals for all milestones (Netlist, GDS, RTL,
IntGuide, MAS, FW Doc)
A collaborative model that drives transparency, efficiency, and successful IP delivery.
Nova
Rays
Semi
© 2026 NovaRays Semi. All rights reserved.
Precision Engineering & Semi-Conductor Systems.
© 2026 NovaRays Semi. All rights reserved.
Precision Engineering & Semi-Conductor Systems.
SPECIALIZED ENGINEERING SERVICES
Engineering
Excellence from
Architecture to
Silicon
Complex Analog and Mixed Signal IP Design Services, from concept to
silicon, and product engineering. Every KPI is optimized for a product with
special focus on quality and predictability.
120+
Years Combined Experience
50+
Silicon Products Delivered
10+
Process Nodes
100+
Successful Tape-outs
Engagement Models Tailored to Your Program
Flexible, transparent, and quality-driven engagement frameworks to meet your exact IP
development needs.
Orientation Change
Transforming the Base IP to different orientations to fit specific
layout requirements.
Aspect Ratio adjustments
Complete Orientation flipping
Configuration (e.g., No of Lanes)
Same or Better KPI (Power performance Area) than original IP
Same or different process node
Process porting
Derivative of existing IP to different foundry processes achieving
same or better KPIs.
Any Process to Any Process Port
Improved KPI (Power, Perf, Area)
CO-VAL with existing Phy
Addressing process driven design changes
Along with Physical (Orientation/Aspect Ratio) change
Custom Feature Addition
Feature addition, and deep Performance/Power/Area Optimization
for existing designs.
Incorporation of product driven Logic/Circuit features
Post Silicon driven ECO's
DFT & SCAN improvements
Improvement of one or more IP KPI
Built to spec
New IP development based on spec/requirements from
Architecture to Tapeout.
End to End ownership (Arch to implementation to product
Engg)
Post-Si Debug and productization
Complete FW and package development
IP KPI improvements
Portfolio Progression
2026
2027
2028
IP
TURNKEY-CUSTOM IP
BASE IP
Process Port
Orientation Change
Feature Addition
IP Optimization
Base IP
UCIe
2026
2026
2026
2026
2028
PCIe
2026
2026
2026
2026
2028
DDR/HBM
2026
2026
2026
2026
2028
PLL
2027
2027
2027
2027
2028
GPIO
2027
2027
2027
2027
2027
Turnkey Custom IP:
Base IP modifications for Process/PHYS change, Feature add,
PPA improvements/etc.
Turnkey Base IP:
New IP based on spec/requirements given by customer on
targeted process and PPA.
Customer Engagement Model
A collaborative model that drives transparency, efficiency, and successful IP delivery.
1. DESIGN ENABLER
Client Responsibilities
Compute
Provide compute infrastructure (Login Access, Machines,
Memory)
Tools and Methodology
Provide EDS tools and methodology (Licenses, Setup files)
Technology Enablers
Provide Technology Collaterals (PDK, Library, etc)
NovaRays Responsibilities
Infrastructure Utilization
Utilizes provided compute infrastructure for development
Tool Execution
Uses provided EDS tools and methodology for IP development
IP Development
Leverages technology collaterals for IP development
2. RECEIVABLES & DELIVERABLES
Client Responsibilities
Pre-Design Collaterals
Provide Source IP Collaterals (Schematic, RTL, Layout, Timing
Constraints, IntGuide)
NovaRays Responsibilities
Milestone Delivery
Deliver IP Collaterals for all milestones (Netlist, GDS, RTL,
IntGuide, MAS, FW Doc)
A collaborative model that drives transparency, efficiency, and successful IP delivery.
© 2026 NovaRays Semi. All rights reserved.
Precision Engineering & Semi-Conductor Systems.
© 2026 NovaRays Semi. All rights reserved.
Precision Engineering & Semi-Conductor Systems.